The schematic diagram of a FET Volt Meter using difference amplifier is shown in Figure. The two FETs are identical so that increase in the current of one FET is offset by corresponding decrease in the source current of the other. The two FETs form the lower arms of the balanced bridge circuit whereas the two drain resistors RD form the upper arms. The meter movement is connected across the drain terminals of the FETs.
The circuit is balanced under zero-input-voltage condition provided the two FETs are identical. In that case, there would be no current through M. Zero-Adjust potentiometer is used to get null deflection in case there is a small current through M under zero-signal condition. Full-scale calibration is adjusted with the help of variable resistor R.
When positive voltage is applied to the gate of F1, some current flows through M. The magnitude of this current is found to be proportional to the voltage being measured. Hence, meter is calibrated in volts to indicate input voltage.
The circuit is balanced under zero-input-voltage condition provided the two FETs are identical. In that case, there would be no current through M. Zero-Adjust potentiometer is used to get null deflection in case there is a small current through M under zero-signal condition. Full-scale calibration is adjusted with the help of variable resistor R.
When positive voltage is applied to the gate of F1, some current flows through M. The magnitude of this current is found to be proportional to the voltage being measured. Hence, meter is calibrated in volts to indicate input voltage.